1. Technical Field
Example embodiments of the present invention relate in general to a field of signal generation, and more particularly, to a duty ratio controlling apparatus for controlling a duty ratio at a predetermined ratio.
2. Related Art
A phase locked loop (PLL) circuit represents a circuit that consistently compares a reference clock with an output clock in phase, and based on the comparison result, corrects a frequency, so that the output clock maintains a constant frequency. The PLL circuit is one of basic circuits generally provided in an electronic system.
In general, the PLL circuit includes a phase frequency detector that compares a phase of an input clock signal with a phase of a comparison signal, a charge pump that provides a current signal having a level corresponding to the comparison result of the phase frequency detector, a loop filter that removes a high frequency component from the current signal provided by the charge pump and converts the current signal into a voltage signal to be output, a voltage controlled oscillator that outputs a clock signal having an oscillation frequency corresponding to the voltage signal provided by the loop filter, and a divider that divides the clock signal output from the voltage controlled oscillator by a predetermined divide ratio to generate a comparison signal, and provides the generated comparison signal to the phase frequency detector.
Due to the structure of such a PLL circuit, noise characteristics of an input signal used as an input to the PLL circuit exert a great influence on noise characteristics of an output signal of the PLL circuit.
Equation 1 describes noise characteristics of a phase of an output signal relative to an input clock signal in a PLL circuit.Lin-band=L1Hz+20 log(Fpll)−10 log(Fref)  [Equation 1]
In Equation 1, Lin-band represents a level of in-band phase noise, and L1Hz is a value, determined by a reference input signal, input into a PLL circuit, that is unchangeable on a circuit. In addition, Fref represents a frequency of the reference input signal, and Fpll represents a frequency of an output signal of the PLL circuit. When assuming that a division factor of a divider included in the PLL circuit is N, a relation is established as Fpll=Fref×N.
Through Equation 1, it is known that the in-band noise of the PLL decreases when the frequency Fref of the reference input signal input into the PLL circuit is doubled.
Accordingly, in order to reduce the in-band noise of the PLL circuit, the frequency is doubled by multiplying the reference input signal. However, if a multiplier that multiplies the frequency of the reference input signal fails to precisely perform the multiplication, Equation 1 is not satisfied and the phase noise characteristics are more aggravated.